The present invention relates to Field Effect Transistor (FET) devices formed of semiconductor nanowires and to a method to fabrication thereof. More particularly, the present invention relates to vertical FET devices with electroplated semiconductor nanowires integrated into three dimensional devices and methods of manufacture thereof.
Improvements in semiconductor FETs have traditionally been implemented by scaling down the relative device dimensions. However, because of fundamental scaling limits, advanced FETs rely increasingly on nontraditional materials and structures and special integration schemes to achieve desired improvements in circuit performance. High-mobility channel FETs in which the channel material comprises a high-mobility material such as germanium instead of silicon (as is traditional) are an example of a type of FET incorporating nontraditional materials. Nanowire based FETs in which a semiconductor nanowire is used as the device channel are known to exhibit quantum confinement effect and an improved device performance. Furthermore, the integration of vertical FETs in a three dimensional fashion has been another nontraditional method to improve the device performance at the system level.
Inorganic semiconductor nanowires can be readily grown by a Chemical Vapor Deposition (CVD) process. Individual inorganic nanowire based FETs have been studied previously. Such transistors are generally fabricated by growing a forest of wires, collecting wires in a liquid suspension, randomly distributing the wires on a substrate, and making contacts to the individual wires to form horizontal devices. Recently, vertical nanowire based field-transistor devices are fabricated in which nanowires of inorganic semiconductors such as Si, ZnO, In2O3 and InAs are grown by CVD processes (see V. Schmidt et al, Small, vol. 2, p. 85 (2006); J. Goldberger et al, Nano Letters, vol. 6, p. 973 (2006); T. Bryllert, Nanotechnology, vol. 17, p. S227 (2006); T. Bryllert, IEEE Electron Device Letter, vol. 27, p. 323 (2006); H. T. Ng et al, “Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor” Nanotechnology Letters, vol. 4, pp 1247-1252 (2004); and P. Nguyen et al, “Direct Integration of Metal Oxide Nanowire in Field-Effect Nanotransistor”, American Chemical Society, Nano Letters, vol. 4, (4) pp 651-657 (2004). The CVD growth of the nanowires starts from a catalytic particle. Therefore in principle, the vertical devices such fabricated can be precisely placed at desired locations and the diameter of the nanowires can be controlled by controlling the location and size of the catalytic particles. However, the catalytic particles are in most cases present in a liquid form at the temperature of nanowire growth and agglomerate. The performance of the devices becomes hard to control as a result of the variation in the nanowire diameter.
Electroplated wide band-gap compound semiconductor, CuSCN, formed in a polymer membrane are described in J. Chen et al, “Vertical nanowire transistors with low leakage current”, Applied Physics Letter, vol. 82, p. 4782 (2003); and vol. 85, p. 1401-1403 (2004). The devices described therein generally suffer from the poor controllability of the processes. A FET fabricated using the process in the prior-art has limited options for the channel geometry, the properties of the dielectrics, the properties of the gate electrode material and the properties of the source and drain electrodes.
A polymer template having randomly located pores was described in a paper by Heydon et al., entitled “Magnetic Properties of Electrodeposited Nanowires” J. Phys. D: Appl. Phys. Vol. 30, No. 7, pp 1083-1093 (1997), and the semiconductor nanowire devices formed were also randomly distributed and the integration of the devices was impossible. In addition, the wide band-gap compound semiconductor, CuSCN, limited the variation and applications of the devices. See also an article by Martin, entitled “Nanomaterials: A Membrane-Based Synthetic Approach” Science Vol. 266, No. 5193, pp. 1961-1966 (1994); and an article by Whitney et al., entitled “Fabrication and Magnetic Properties of Arrays of Metallic Nanowires”, Science Vol 261, No. 5126, pp. 1316-1319 (1993).
Methods of forming germanium epitaxial structures, including germanium nanowires by electroplating are described in a copending U.S. patent application Ser. No. 11/620,224 of S. W. Bedell et al entitled “Structures Containing Electrodeposited Germanium and Methods for Their Fabrication” filed 5 Jan. 2007, and a copending U.S. patent application Ser. No. 11/620,391 of H. Deligianni et al. “Self-Constrained Anisotropic Germanium Nanostructure from Electroplating” also filed 5 Jan. 2007, which are commonly assigned to the assignee of the present application.
U.S. Pat. No. 6,838,297 of Iwasaki et al. entitled “Nanostructure, Electron Emitting Device, Carbon Nanotube Device, and Method of Producing the Same” describes a nanostructure including an anodized film with nanoholes cut completely through the anodized film from the surface of the anodized film to the surface of the substrate. The anodized film is formed on a substrate having a surface including a material including semiconductors, noble metals, Mn, Fe, Co, Ni, Cu and carbon. The nanoholes have variable diameters such as a constriction at a location between the surface of the anodized film and the surface of the substrate. After producing the nanoholes on the n-type silicon substrate and performing the pore widening process in a similar manner to the second embodiment, Co was electro-deposited thereby forming catalytic fine particles inside the nanoholes. Subsequently, the sample was heated at 700° C. for 1 hour in a mixed gas of 2% C2H4 and 98% He so that carbon nanotubes were grown from the catalytic ultra-fine particles. Carbon nanotubes, which bristle outwardly at different angles from the inside of the nanoholes had diameters of the carbon ranging from 2 nm to 50 nm and they were tilted at different angles and had very substantially smaller diameters than the nanoholes.
FIG. 1A is a schematic diagram of a prior art horizontal FET 10 formed on a semiconductor substrate 20 composed of a material such as silicon, germanium and gallium arsenate. The substrate 20 is properly doped according to the type of the devices, e.g., n-FET or p-FET. There are source and drain electrodes 30 located at both ends of the FET 10. The very top region of the substrate 20 between the source and drain electrodes 30 is the channel 40 of the FET 10. The on-off state of the FET 10 is controlled by a gate electrode 50 located above the channel region 40. A gate dielectric layer 60 is present between the channel 40 and the gate electrode 50. The sidewall of gate electrode is separated from other parts of the device by a spacer layer 70.
FIG. 1B is a schematic diagram of a prior art vertical FET 100 built from a semiconductor nanowire grown by a CVD process as described in T. Bryllert et al., entitled “Vertical High-Mobility Wrap-Gated InAs Nanowire Transistor”, IEEE Electron Device Letters, 27(5), pp 323-325 (2006.) The transistor 100 includes a channel 120 comprising a semiconductor nanowire grown by CVD processing on a substrate 110 which also serves as the source electrode. After the growth of the semiconductor nanowire 120, a gate dielectric layer 150 is deposited around the semiconductor nanowire 120. Then at a middle portion of the semiconductor nanowire 120, a gate electrode 140 is fabricated wrapped about the gate dielectric 150 and the semiconductor nanowire 120 within the gate dielectric 150. A drain electrode 130 is fabricated with a special process so that it covers the top part of the semiconductor nanowire 120. The gate electrode 140 is separated from the source electrode 110 and the drain electrode 130 by spacer layers 160 which are deposited on the surface of the substrate 110 and surrounding the gate electrode 140. A contact line 130 is connected to the top of the semiconductor nanowire 120. The gate is supported by the gate dielectric layer 150 and the spacer layers 160.
The semiconductor nanowires of Bryllert et al. which are formed on a chip are fabricated by using metal particles as seeds for anisotropic epitaxial growth of semiconductor nanowires using a Chemical Vapor Deposition (CVD) system. The device fabrication is performed on the semiconductor nanowire afterwards. The metal gate is formed by first depositing SiNx as gate dielectric on the wires. Then the gate metal is deposited using sputtering covering the whole wires with SiNx and gate metal. In order for the gate wrapping to be present only around the base of the wires, the chip is spin coated with an organic film. The film is then etched back to expose the tops of the wires. The gate metal is etched away from the top of the wires. A gate pad and the gate finger are defined by optical lithography and wet etching. A drain contact which wraps around the top of the wires, is fabricated with an airbridge technology. The source contact is provided by an InAs substrate. The fabrication process continues with wires with wrap gates formed thereon.
U.S. Pat. No. 7,230,286 of Cohen et al. entitled “Vertical FET with nanowire channels and a silicided bottom contact” which is commonly assigned describes a vertical FET structure with nanowires forming FET channels on a bottom, epitaxial, conductive silicide layer which is epitaxial and conductive. The nanowires are grown perpendicular to the bottom conductive layer. A source and a drain are located at each end of the semiconductor nanowires with a channel therebetween. A gate dielectric surrounds the channel of each semiconductor nanowire and a gate conductor surrounds the gate dielectric. Top and bottom insulator plugs function as gate spacers and reduce the gate-source and gate-drain capacitance. Catalyst dots such as Au, Ga, Al, Ti, and Ni for the nanowire growth are formed over the exposed silicide layer. The widths of the catalyst dots define the nanowire diameters. The growth of the nanowires, which is assisted by the catalyst dots and is typically carried out by CVD or Plasma Enhanced Chemical Vapor Deposition (PECVD) using silane or silicon tetrachloride. Note that the nanowires can be comprised of the same or different material from that of the semiconductor substrate.
In one embodiment, it is preferred that the nanowires should be comprised of a material that is different from the semiconductor substrate. In yet another embodiment of the invention, the nanowires are single-crystal Si nanowires having substantially the same crystal orientation. Si nanowires can be formed on a (111) oriented Si substrate, the silicon nanowires orientation is (111) as it is seeded from the substrate which also has the (111) orientation. Thus a silicide film which mimics the substrate orientation is used. While the Cohen patent teaches vertical FETs made from nanowires, they are not formed in nanopores which control the configuration of the nanowires and the nanowires are not in contact with the lower dielectric layer containing the nanopores. The FETs therein comprise multiple nanowires and therefore they comprise multiple device channels.
In the prior art shown in FIG. 1B, the semiconductor nanowires, which were grown by CVD process, were free standing and fragile after growth thereof. The Cohen et al. semiconductor nanowires which were grown by CVD or PECVD are also freestanding grown without any support and accordingly they are also fragile. Therefore the processes for fabrication of such free standing nanowires is intrinsically challenging in order to avoid damaging the wires during processing.